Accelerated Techniques in Stem Fault Simulation  

作　　者：石茵 魏道政 

机构地区：[1]CADLaboratory,InstituteofComputingTechnology,ChineseAcademyofSciencesBeijing100080 [2]CADLaboratory,Inst

出　　处：《Journal of Computer Science & Technology》1996年第6期551-561,共11页计算机科学技术学报（英文版）

摘　　要：In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques,the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectivenbss improves obyiously.In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques,the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectivenbss improves obyiously.

关 键 词：Fault simulation critical path tracing parallel pattern evaluation stem fault simulation explicit fault simulation 

分 类 号：TN32[电子电信—物理电子学]