MADET-A Machine-Description Table Based Instruction Scheduler in TH-RISC for Exploiting Instruction Level Parallelism  

作　　者：李三立 付兴钢 

机构地区：[1]DepartmentofComputerScienceandTechnology,TsinghuaUniversity,Beijing100084 [2]DepartmentofComputerScience

出　　处：《Journal of Computer Science & Technology》1994年第2期153-159,共7页计算机科学技术学报（英文版）

摘　　要：This paper presents a parameterized instruction scheduling algorithm based on machine description table for TH-RISC system, having a (3-5) stages pipeline structure.It would provide considerable fiexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. Alld, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analyzed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem, the improvement of instruction level parallelism (ILP) and speed-up results are given.The algorithm complexity is O(n2).This paper presents a parameterized instruction scheduling algorithm based on machine description table for TH-RISC system, having a (3-5) stages pipeline structure.It would provide considerable fiexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. Alld, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analyzed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem, the improvement of instruction level parallelism (ILP) and speed-up results are given.The algorithm complexity is O(n2).

关 键 词：Instruction level parallelism machine description table instruction scheduler TH-RISC 

分 类 号：TN47[电子电信—微电子学与固体电子学] TP338[自动化与计算机技术—计算机系统结构]