高速双模前置分频器的速度优化设计  

The circuit design of speed optimization for a high-speeddual-modulus prescaler

作　　者：邝小飞[1] 

机构地区：[1]零陵学院物理系,电子信息工程系,湖南永州425006

出　　处：《半导体技术》2002年第10期38-42,共5页Semiconductor Technology

摘　　要：给出了一种新的高速动态有比CMOS　D触发器的设计。在分析64/65双模前置分频器工作原理的基础上,提出了提高其工作速度的方法,运用单相时钟(TSPC)动态CMOS、伪NMOS等电路技术,设计了多种内部电路结构。经HSPICE模拟,在0.8mmCMOS工艺、电源电压为5V的条件下,最高时钟频率达到了1.7GHz,其速度和集成度远远超过静态CMOS电路。A new high-speed, ratioed, dynamic CMOS D flip-flop is presented . Based on theanalysis of the 64/65 dual-modulus presaler, the methods as well as circuit architectures using truesingle-phase-clock(TSPC) dynamic CMOS and pseudo NMOS technology are put up with for theimprovement of its speed. By the HSPICE simulation, the maximum operating clock frequency hasreached as high as 1.7GHz in the 0.8mm CMOS technology and 5V supply voltage, which is signifi-cantly improved compared with the static CMOS circuits.

关 键 词：高速双模 前置分频器 速度优化设计 最高时钟频率 CMOS电路设计 锁相环 频率合成器 

分 类 号：TN772[电子电信—电路与系统]