三维IP核测试封装扫描链多目标优化设计  

3D IP core test wrapper scanning chain design based on multi-objective algorithm

作　　者：朱爱军[1] 李智[1,2,3] 许川佩[2] 

机构地区：[1]西安电子科技大学机电工程学院,西安710071 [2]桂林电子科技大学电子工程与自动化学院,桂林541004 [3]桂林航天工业学院,桂林541004

出　　处：《电子测量与仪器学报》2014年第4期373-380,共8页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金(60766001)资助项目;广西自动检测技术与仪器重点实验基金(YQ14110)项目资助

摘　　要：SoC(system on chip)中的测试封装(test wrapper)设计是个NP hard问题,针对该问题提出了一种采用MOFA(multiobjective firefly algorithm)的三维测试封装扫描链设计方法,使得封装扫描链均衡化以及使用TSV(through silicon vias)资源最少,从而达到IP核测试时间最小化和TSV费用最少的目的。本算法基于群体智能,通过实施个体位置更新操作进行寻优,从而实现三维测试封装扫描链的多目标优化设计。以ITC'02 Test benchmarks中的典型IP核为实验对象,实验结果表明本算法相比NSGAII(nondominated sorting genetic algorithm II),能够获得更好的Pateto最优解集。Test wrapper design in SoC is a NP hard problem.This paper proposes a MOFA(multi-objective firefly algorithm) algorithm for the three dimension test wrapper scanning chain design,which can make wrapper scan chain equalization and use less TSV,so as to achieve the purpose of minimization of the IP core test time and the number of TSV used.The algorithm,which is based on swarm intelligence,through the implementation of location updating operation,can achieve equalization of the wrapper scanning chain and use less TSV resource.Typical IP cores in ITC'02 benchmarks are adopted,and the experimental results show that the algorithm can obtain better Pateto Set compared to NSGAII(nondominated sorting genetic algorithm II),thereby reduce the test cost of the IP core.

关 键 词：多目标优化 封装扫描链 SOC测试 

分 类 号：TN47[电子电信—微电子学与固体电子学]