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机构地区:[1]安徽理工大学计算机科学与工程学院 [2]江苏南通商贸职业学校信息系
出 处:《电子测量与仪器学报》2018年第4期187-192,共6页Journal of Electronic Measurement and Instrumentation
基 金:国家自然科学基金(61404001,61306046);国家自然科学基金面上项目(61371025)资助;安徽省高校省级自然科学研究重大项目(KJ2014ZD12);淮南市科技计划(2013A4011)
摘 要:负偏置温度不稳定性(NBTI)效应促使晶体管的阈值电压不断升高,老化加剧,最终造成电路时序违规。现有的用于缓解由NBTI引起的电路老化插入传输门(TG-based)技术,在获取关键门时只考虑电路中单条路径的老化情况,而未考虑门与保护路径之间的相关关系,因此获取的关键门存在冗余。针对这一问题,在充分考虑门与保护路径之间的相关关系后,定义权值,更加精准的识别路径中的关键门集合,再对关键门进行插入传输门保护。实验结果显示,当电路的时序余量为5%时,电路的平均时延改善率为38.18%,面积开销相比现有方案平均改善了61.8%。Negative bias temperature instability( NBTI) effect causes the transistor threshold voltage to rise continuously,increasing aging,and eventually resulting in circuit timing violation. The existing transmission gate insertion technology( TG-based),which is used to mitigate the circuit aging caused by NBTI,only takes into account the aging of the circuit under the single path,without considering the correlation between the gates and the protected paths when acquiring the critical gates,so the critical gates are redundant. To solve this problem,after considering the correlation between the gates and the protected paths,the weights are defined,the critical gates in the paths are more accurately identified,and then the critical gates are protected by inserting transmission gates. The experimental results show that when the time margin of the circuit is 5%,the average delay improvement rate of the circuit is 38. 18%,and the area cost is improved by 61. 8% compared with the existing scheme.
分 类 号:TN402[电子电信—微电子学与固体电子学]
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