PC104故障监控平台FPGA程序设计  

FPGA program design of PC104 fault monitoring platform

作　　者：周治虎 张凡[1,2] 武明虎 孔祥斌[1,2] 刘聪 代松[1,2] 

机构地区：[1]湖北工业大学太阳能高效利用湖北省协同创新中心,湖北武汉430068 [2]湖北省电网智能控制与装备工程技术研究中心,湖北武汉430068

出　　处：《电子技术应用》2017年第9期57-60,共4页Application of Electronic Technique

基　　金：国家自然科学基金(61471162;11605051;61601177);国家国际科技合作专项(2015DFA10940)

摘　　要：PC104总线是专为嵌入式控制系统定义的一种工业控制线,其应用广泛,但是内部结构复杂,出现故障不易检测。设计了一种基于FPGA的PC104总线故障自动监控平台,对PC104总线信号进行实时监控和故障检测。该平台利用FPGA程序采集和处理总线信号,并传至上位机处理显示。系统中利用FPGA程序实现其功能模块,包括捕获POST上电自检指令和BIOS自检端口代码、监测总线电压水平、监控时钟和复位等关键信号的质量、控制PC104的自动复位和BIOS设置模式等功能。给出上位机监控结果和FPGA实时检测得到的时序图,反映了该FPGA程序在本系统中满足PC104总线检测的技术要求。PC104 bus is a specifical industrial control line and defined for embedded control system, and its widely used. But it′s difficult to measure when the fault occurs because of the internal structure of complex. This paper designs a fault automatic moni-toring platform which is based on FPGA for PC104 bus, the platform monitors the PC104 bus signal and detects the fault in real-time. The platform uses the FPGA program to collect and process the bus signal, and send to the host computer processing to dis-play in time. The functional modules are achieved by FPGA in this system, which are including capture the POST self-test command and BIOS self-test port code, monitor bus voltage level, measure the quality of key signals such as clock and reset, and control PC104 auto reset and BIOS setup mode. Finally, the paper publishes the PC monitoring results and FPGA real-time detec-tion of the timing diagram to reflect the FPGA program in the system can meet the PC104 bus detection technology requirements.

关 键 词：总线监测 POST上电自检 自检端口监测 时钟测量 

分 类 号：TN79[电子电信—电路与系统] TP273[自动化与计算机技术—检测技术与自动化装置]