基于流水线技术的全数字锁相环设计  

Design of all-digital phase-locked loop based on pipeline technology

作　　者：田帆 杨檬玮 单长虹[1] Tian Fan;Yang Mengwei;Shan Changhong(College of Electrical Engineering,University of South China,Hengyang 421001,China)

机构地区：[1]南华大学电气工程学院,湖南衡阳421001

出　　处：《电子技术应用》2019年第4期39-44,共6页Application of Electronic Technique

基　　金：湖南省教育厅重点项目资助(14A119)

摘　　要：为了提高全数字锁相环的系统运行速度、降低系统功耗,同时提高锁相系统的动态性能与稳态性能,提出一种基于流水线技术的全数字锁相环。采用电子设计自动化技术完成了该系统的设计,并对所设计的电路进行了计算机仿真与分析。仿真结果证明,该锁相环中数字滤波器的参数能够根据相位误差的大小进行动态调节,既可加快锁相速度,又能增强系统的稳定性。利用流水线技术优化的整体电路能够减小系统延迟,降低系统总功耗。该锁相环可作为功能模块嵌入到片上系统,具有十分广泛的用途。Absrtact:In order to improve the system of full digital phase-locked loop speed,reduce the power consumption of the system,and at the same time improve the dynamic performance and steady-state performance of phase-locked system,this paper proposes a full digital phase-locked loop based on assembly line.The electronic design automation technology is used to complete the design of the system,and the designed circuit is simulated and analyzed by computer.Simulation results show that the parameters of the digital filter in the phase-locked loop can be dynamically adjusted according to the magnitude of phase error,which can not only speed up the phase-locked speed,but also enhance the stability of the system.The integrated circuit optimized by pipeline technology can reduce the system delay and reduce the total power consumption.The phase-locked loop can be embedded as a functional module into SoC(Systerm on Chip)and has a wide range of applications.

关 键 词：全数字锁相环 电子设计自动化 超高速集成电路硬件描述语言 计算机仿真 流水线 

分 类 号：TN911.8[电子电信—通信与信息系统]