频域LMS自适应滤波器的Systolic阵列结构研究  

Study on Systolic Array Architecture of Frequency Domain LMS Adaptive Filter

作　　者：吴晓蕙[1] 陆跃[1] 何振亚[1] 

机构地区：[1]东南大学

出　　处：《通信学报》1991年第4期49-53,共5页Journal on Communications

摘　　要：本文提出了一种实现频域LMS自适应滤波器的Systolic阵列结构。该阵列结构中引入了多速率技术,对于自适应滤波器中的DFT变换和IDFT变换分别采用串入-并出方式和文中提出的并入-串出方式加以实现。整个结构的突出优点是结构简单、基本单元少、占用芯片面积少。In this paper, one kind of systolic array architecture for frequency domain LMS adaptive digital filter is proposed. The DFT and the IDFT in the adaptive filter systolic array are realized respectively by serial-input and parallel-output mode and paralell-input and serial-output mode which is a new mode developed by the authors. The architecture uses the multiple clock cycle technique and has advantages of high parallelism, modularity, regularity, less basic cells, less chip area and nearest neighbor interconnections.

关 键 词：自适应滤波器 结构 频域LMS 

分 类 号：TN911.72[电子电信—通信与信息系统]