基于Verilog-XL的传输晶体管逻辑模拟  

Logical simulation of pass-transistor with Verilog-XL

作　　者：裴志军[1] 国澄明[1] 姚素英[1] 

机构地区：[1]天津大学,天津300072

出　　处：《半导体技术》2002年第11期38-41,共4页Semiconductor Technology

摘　　要：随着集成电路集成度的持续增加,集成电路设计也越来越复杂,这使得设计验证愈来愈重要。模拟作为验证的重要手段在集成电路设计EDA系统中广泛采用,如Verilog-XL是Cadence EDA 系统工具箱中的优秀模拟器,可作为传输晶体管逻辑设计的有效模拟工具。The integrated circuit design is becoming more complicated with continuousincrement of the integrated degree, so the simulation,as one of the important means for the de-sign verification, is adopted by most integrated design EDA system. Verilog-XL, being an excellentsimulator integrated into Cadence EDA system, can be used in the simulation of pass-transistorlogic design.

关 键 词：Verilog-XL 集成电路 模拟 传输晶体管 硬件描述语言 

分 类 号：TN407[电子电信—微电子学与固体电子学]