A Low Power/Area Digital FIR Filter Design Based on PRF Framework  

作　　者：王栋 Wang Wei Xu Xiaoming 

机构地区：[1]Institute of Intelligent Control,Shanghai Jiaotong University,Shanghai 200030, P.R.China

出　　处：《High Technology Letters》2002年第3期57-61,共5页高技术通讯（英文版）

基　　金：SponsoredbyHDTVProjectofStateDevelopmentPlanningCommissionP .R .China

摘　　要：A novel DSP to ASIC (Application Specific Integrated Circuit) architecture design methodology is presented in this paper for reducing power/area consumption. Traditional methods always focus on optimizing hardware structure or algorithm separately. The authors propose a new method called PRF (Paralleling Reducing Folding) framework to combine hardware optimization with algorithm simplification. In the first step, paralleling, unfolding technology is applied to divide one data path into several channels and expose the redundancy of the algorithm. In the second step, reducing, decoupling theory is used to reduce computational complexity. In the last step, folding, time multiplexing method is used to merge similar components. As an exoteric methodology framework, many optimization methods can be integrated into the PRF framework. To optimize a 3N taps FIR (Fincte Impact Response) and obtain a content result, PRF methodology framework is applied.A novel DSP to ASIC (Application Specific Integrated Circuit) architecture design methodology is presented in this paper for reducing power/area consumption. Traditional methods always focus on optimizing hardware structure or algorithm separately. The authors propose a new method called PRF (Paralleling Reducing Folding) framework to combine hardware optimization with algorithm simplification. In the first step, paralleling, unfolding technology is applied to divide one data path into several channels and expose the redundancy of the algorithm. In the second step, reducing, decoupling theory is used to reduce computational complexity. In the last step, folding, time multiplexing method is used to merge similar components. As an exoteric methodology framework, many optimization methods can be integrated into the PRF framework. To optimize a 3N taps FIR (Fincte Impact Response) and obtain a content result, PRF methodology framework is applied.

关 键 词：ASIC architecture systolic array paralleling reducing folding power/area optimization 

分 类 号：TN402[电子电信—微电子学与固体电子学]