基于FPGA的数字水印提取系统设计研究  

Design of digital watermark extraction system based on FPGA

作　　者：刘晓彦 LIU Xiaoyan(Changchun University of Science and Technology,Changchun 130600,China)

机构地区：[1]长春科技学院,吉林长春130600

出　　处：《现代电子技术》2016年第15期62-66,共5页Modern Electronics Technique

摘　　要：针对信息安全问题的日益突出,提出了基于5/3整数小波的数字水印算法,给出了两种5/3小波的硬件架构:一种是基于RAM的流水线架构;另一种是基于行分组的行列并行架构。进而设计了基于FPGA的数字水印提取硬件系统,结果证明该算法具有很好的不可见性及鲁棒性,且复杂度低,硬件较容易实现,并将水印提取代码下载到FPGA硬件进行验证,结果证明该算法可以很好地实现水印的提取工作。Since the information security problem has become increasingly prominent,a digital watermark algorithm basedon 5/3 integers wavelet is proposed. Two hardware architectures of 5/3 wavelet are given:one is the pipelined architecture basedon RAM,and the another is the rank parallel architecture based on row grouping. The hardware system of digital watermark ex?traction based on FPGA was designed. The results show this algorithm has good invisibility,robustness and low complexity,andis easy to implement with hardware. The wartermark extraction code is downloaded to FPGA for hardware verification. The verifi?cation results show that the system can extract the digital watermark well.

关 键 词：数字水印 5/3小波 FPGA 水印提取 

分 类 号：TN915.08[电子电信—通信与信息系统] TP37[电子电信—信息与通信工程]