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作 者:秦昳[1] 史晓楠[1] 巨新刚[2] QIN Yi;SHI Xiaonan;JU Xingang(School of Computer Science and Technology,Xi’an University of Science and Technology,Xi’an 710054,China;Xi’an Microelectronics Technology Institute,Xi’an 710065,China)
机构地区:[1]西安科技大学计算机学院,陕西西安710054 [2]西安微电子技术研究所,陕西西安710065
出 处:《现代电子技术》2016年第16期83-87,共5页Modern Electronics Technique
基 金:陕西省教育厅科研计划项目资助(14JK1469)
摘 要:针对多核处理器的特点提出一种新型的异构多核DSP处理器结构。主处理器为通用处理器,作为控制密集型处理器核用于系统管理和控制;8个DSP作为计算密集型处理器核,用于大信息量融合计算。详细设计8个DSP之间的No C互连结构。首先采用2×4 2D Turos结构进行单个路由节点结构的设计,包括数据包格式、路由和仲裁设计;其次对路由节点进行编码、路由算法设计和确定节点路由方向。该结构具有总线局部通信带宽高的优点,采用No C的易扩展性和No C在各DSP之间通信的并行性使系统规模易于扩展并满足大批量数据传输要求。最后通过仿真实验,验证了该设计的有效性,为后续多核处理器的设计与实现打下坚实的技术基础。Aiming at the characteristics of multi?core processor,a new heterogeneous structure of multi?core DSP is put for?ward. The main processor is a common processor used for system management and control to control the intensive processorcores. Eight DSPs as the computation intensive processor cores are used to fuse and calculate the large amount of information.The structure of NoC interconnection among 8 DSPs was designed detailedly. The 2×4 2D Turos structure is used to design thesingle routing node structure,including data packet format design,routing design and arbitration design. And then the items ofrouting nodes coding,routing algorithm design and node routing direction determining were performed. This structure has the ad?vantage of high bus local communication bandwidth. The extensibility of NoC and parallelism of NoC communication amongDSPs are used to extend the system scale easily and satisfy the requirement of massive data transmission. The validity of the de?sign was verified with simulation experiment,and it lays a solid technical foundation for follow?up design and implementation ofmulti?core processors.
分 类 号:TN911.34[电子电信—通信与信息系统] TP391[电子电信—信息与通信工程]
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