基于MAC单元的低功耗低延时FIR滤波器的设计与分析  

Design and analysis of low-power consumption and low-latency FIR filter based on MAC unit

作　　者：李琼[1,2] 杜爱民[1] 曹馨[1] 赵琳[1] 李翠红[1,2] LI Qiong;DU Aimin;CAO Xin;ZHAO Lin;LI Cuihong(Key Laboratory of Earth and Planetary Physics,Institute of Geology and Geophysics,CAS,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院地质与地球物理研究所地球与行星重点实验室,北京100029 [2]中国科学院大学,北京100049

出　　处：《现代电子技术》2016年第16期155-158,共4页Modern Electronics Technique

基　　金：中国国家基础研究发展计划(2014CB845903;2012CB825604);国家R&D关键科学仪器项目(ZDYZ2012-1-01)

摘　　要：乘法器在数字信号处理系统中承担了很重要的作用,而乘法器消耗相当大的功耗,因此有必要进行乘法器的低功耗研究。介绍一种基于乘法累加(MAC)单元的FIR滤波器的设计,其中乘法器利用基4华莱士树乘法器,加法器利用超前进位加法器,在优化整合之后,得到低延时低功耗FIR滤波器。实验证明,该文设计的FIR滤波器具有很小的延时与很低的动态功耗。The multiplier unit plays an important part in digital signal processing system,but it has considerable power con?sumption,so it is necessary to research the low?power consumption of the multiplier unit. A design of FIR filter based on multi?plier and accumulator(MAC)is introduced. The multiplier uses the radix?4 Wallace tree multiplier,and the accumulator usesthe carry lookahead adder(CLA). After the optimization and integration,a low?latency and low?power consumption FIR filterwas obtained. The experimental results show that the designed FIR filter has very low latency and dynamic power consumption.

关 键 词：有限冲激响应滤波器 MAC单元 动态功耗 延时 

分 类 号：TN713.34[电子电信—电路与系统]