面向标准单元三维布局的密度驱动划分方法  

Density-Driven Partitioning Method for Standard Cell 3D Placement

作　　者：蒋艳德 刘畅[1] 贺旭[1,2] 郭阳[1] Jiang Yande;Liu Chang;He Xu;Guo Yang(College of Computer, National University of Defense Technology, Changsha 410073;College of Computer Science and Electronic Engineering, Hunan University, Changsha 410082)

机构地区：[1]国防科学技术大学计算机学院,长沙410073 [2]湖南大学信息科学与工程学院,长沙410082

出　　处：《计算机辅助设计与图形学学报》2016年第11期2021-2026,共6页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(61133007;61402505)

摘　　要：标准单元布局是超大规模集成电路自动化设计的一个关键阶段.针对三维布局问题,提出一种面向标准单元的密度驱动划分方法.该方法将三维布局区域划分成网格,并计算每个网格的单元密度,再根据网格单元密度将标准单元合理地划分到三维空间,可有效地减小标准单元与固定单元之间的重叠率,得到优化的划分结果.将文中方法嵌入到三维布局器中,对三维转换的benchmarks电路进行三维布局.实验结果表明,与原始三维布局器3D-Crust相比,该方法能够有效地减少HPWL 60.89%,减少运行时间20.54%.Placement of standard cells is a key stage in very large scale integration circuit design automation. Thisarticle presents a density-driven partitioning method for standard cell 3D placement. In the partitioning method,3D placement region is divided into grids, and the cell density of each grid is calculated. Then the standard cellsare allocated into 3D space based on the cell density in each grid. The partitioning method can get an optimal partitioningresult and reduced the overlaps between standard cells and fixed cells effectively. The partitioning methodis integrated into a 3D placer 3D-Crust, which conducts the 3D placement in 3D-transformed benchmarks.Experimental results show that the partitioning method can effectively reduce HPWL and runtime by 60.89% and20.54% respectively compared with the original placer.

关 键 词：布局 三维集成 VLSI 划分 标准单元 单元密度 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]