基于FPGA的并行数字脉压设计  

Design of parallel digital pulse compression based on FPGA

作　　者：王利华 赵军 汤勇 韩晓明 Wang Lihua;Zhao Jun;Tang Yong;Han Xiaoming(AVIC Leihua Electronic Technology Research Institute, Wuxi 214063, Jiangsu, China)

机构地区：[1]航空工业雷华电子技术研究所,江苏无锡214063

出　　处：《航天电子对抗》2017年第5期42-45,54,共5页Aerospace Electronic Warfare

摘　　要：在超宽带雷达接收系统中,对超大带宽、高数据率和大数据量的基带信号处理,并不再适合采用传统的基于DSP芯片的低速率串行脉压方式。在数字中频接收系统中基于FPGA实现并行多相滤波数字下变频与并行数字脉压的综合设计,采用并行多相FFT和频率抽取IFFT的算法架构,多个并行基带信号同时进行脉压运算,相比传统串行方式能够大大提高处理效率。将数字脉压由雷达信号处理系统提前到数字中频接收系统实现,并基于FPGA实现并行高效处理,对优化雷达系统的接收及处理架构具有重要意义。In the ultra-wideband radar receiving system,processing of the baseband signal for large bandwidth,high data rata and large data volume is not suitable for low-rate serial pulse compression based on digital signal processor(DSP).In digital intermediate frequency(IF)receiving system,the integrated design of polyphase filter digital down conversion(DDC)and parallel pulse compression,using parallel multi-phase fast Fourier transform(FFT)and frequency extraction inverse fast Fourier transform(IFFT)algorithm architecture,a number of parallel baseband branch signal simultaneously implementation pulse compression operation,and greatly improve the processing effectiveness.The implementation of digital pulse compression algorithm from the traditional processing system to the digital IF receiving system,and complete parallel processing based on FPGA,which optimize the receiving and processing system of radar.

关 键 词：并行脉压 并行多相快速傅里叶变换 频率抽取快速傅里叶逆变换 现场可编程门阵列 

分 类 号：TN791[电子电信—电路与系统] TN957.5