基于Nand Flash的BCH校验方法设计与实现  

Design and implementation of BCH verification method based on Nand Flash

作　　者：焦新泉[1] 武慧军[1] 单彦虎[1] 秦菲 Jiao Xinquan;Wu Huijun;Shan Yanhu;Qin Fei(State Key Laboratory of Electronic Testing Technology, North University of China, Taiyuan 030051, China)

机构地区：[1]中北大学电子测试技术国家重点实验室,太原030051

出　　处：《电测与仪表》2017年第22期59-64,共6页Electrical Measurement & Instrumentation

基　　金：国家自然科学基金资助项目(51475437)

摘　　要：针对传统汉明码ECC校验方法纠错能力差的特点,结合Nand Flash闪存内部组织结构,提出一种(4200,4096,8)的BCH码ECC校验方法。该方法采用并行编码方式,且对占用逻辑资源最多的译码器部分采用并行流水线分块译码,极大的提升了编译码效率。以FPGA为验证平台,通过大量数据读写表明,该方法大大提高了存储可靠性,为目前大容量存储提供了参考,具有较高的实用价值。According to the internal structure of the Nand Flash memory and poor correct capability of traditional ECC of Hamming checking method,a kind of(4200,4096,8)BCH code for ECC verification is proposed.Parallel coding mode is chosen in this method,what’s more,parallel pipeline block decoding method is used for the decoder,which occupies most logical resource.With the method above,decoding efficiency is greatly increased.FPGA is selected as the verification platform,verification on this platform shows that the storage reliability is significantly improved through using BCH code for ECC verification.The proposed method has high practical value and provides reference for current large capacity storage.

关 键 词：BCH校验 并行编码 分块译码 FPGA 可靠性 

分 类 号：TM93[电气工程—电力电子与电力传动]