基于FPGA的自顶向下乘法器电路设计  

From Top to Bottom Multiplier Circuit Design Based On FPGA

作　　者：陈楚 吕石磊 孙道宗 刁寅亮 Chen Chu;Lv Shilei;Sun Daozong;Diao Yinliang(College of Electronic Engineering,South China Agriculture University,Guangzhou Guangdong 510642)

机构地区：[1]华南农业大学电子工程学院,广东广州510642

出　　处：《数字技术与应用》2017年第11期165-166,170,共3页Digital Technology & Application

基　　金：广东省公益研究与能力建设专项(2016A020210088)

摘　　要：自顶向下电路设计方法是FPGA电路设计的重要内容,和传统的电子产品设计方法有很大区别,主要是通过EDA软件对电路设计文件进行相关处理,最终实现专用集成电路的设计。本文结合移位相加型乘法器实际例子介绍了两种电路设计输入方式,纯文本输入利用硬件描述语言对底层元件和顶层文件的电路功能进行描述;文本和原理图混合输入对电路的底层元件进行硬件描述语言描述,而顶层文件则采用原理图输入方式来实现。对两种输入方式的仿真波形进行分析,论证了设计方法的正确性,说明了两种输入方式的特点。From top to bottom circuit design mean is the emphasis during FPGA circuit design.There is great difference between this mean and traditional electronic design.From top to bottom circuit design mean processes circuit design file by the EDA software in order to fulfill application specific integrated circuit design.In this paper it introduces two circuit design input means in the shift and accumulate type multiplier example.The pure text input mean describes the top level and bottom level circuit behavior by hardware description language.The composed mean of text input andschematic input describes the bottom level component by hardware description language,on the same time the top level file will be fulfilled by the schematic input.There is analysis of simulate waveform about two different input means,it proves these design means are right and concludes their characteristics.

关 键 词：自顶向下 硬件描述语言 文本输入 原理图输入 乘法器 

分 类 号：TN79[电子电信—电路与系统]