基于粗粒度可重构密码阵列的AES算法映射实现  

IMPLEMENTATION OF AES ALGORITHM MAPPING BASED ON COARSE-GRAINED RECONFIGURABLE CIPHER LOGIC ARRAY

作　　者：李远铭 严迎建[1] 李伟[1] Li Yuanming;Yan Yingjian;Li Wei(PLA Information Engineering University,Zhengzhou 450001,Henan,China)

机构地区：[1]解放军信息工程大学,河南郑州450001

出　　处：《计算机应用与软件》2018年第3期304-308,326,共6页Computer Applications and Software

基　　金：国家自然科学基金项目(61404175)

摘　　要：粗粒度可重构密码阵列CGRCA(Coarse-Grained Reconfigurable Cipher Logic Array)是针对密码算法的加速平台。通过对该阵列的结构进行分析,其具有动态插入寄存器的特点。在此基础上映射实现了AES子密钥生成算法和AES加密算法,并简要阐述映射步骤。面向不同的应用场景,针对AES加密算法分别提出面积最小和流水展开两种映射方式。此外为了充分利用阵列具有的特殊结构,分析轮运算中关键路径的延时差异,选择性插入寄存器,一定程度上提高了算法执行的吞吐率。实验结果表明,通过插入寄存器,两种方式各自吞吐率提高了11.3%和1.9%。通过与其他平台的对比,流水展开方式的实现性能可达其他平台的1.73~7.37倍,具有较好的实现性能。Coarse-grained reconfigurable cipher logic array(CGRCA)is an accelerating platform for cipher algorithms.By analyzing the structure of the array,it has the characteristic of dynamically insertion registers.On the basis,this paper implemented AES sub key generation algorithm and AES encryption algorithm,and described the mapping steps briefly.For different application scenarios,the two methods of minimum area and pipeline expansion were proposed respectively for AES encryption algorithm.In addition,to make full use of the special structure of the array,this paper analyzed delay difference of the critical path in round operation,and inserted register selectively.As a result,the throughput of algorithm was improved.The experimental results showed that by inserting registers,the throughput of each of the two methods increased by 11.3%and 1.9%respectively.Compared with other platforms,the performance of pipelining reached 1.73~7.37 times that of other platforms with better performance.

关 键 词：CGRCA 动态插入 AES 延时差异 吞吐率 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]