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作 者:吕倩茹 王彦鹏 曹壮 文梅[1] LU Qian-ru;WANG Yan-peng;CAO Zhuang;WEN Mei(College of Computer,National University of Defense Technology,Changsha 410073,China)
机构地区:[1]国防科技大学计算机学院,湖南长沙410073
出 处:《计算机工程与科学》2018年第3期381-387,共7页Computer Engineering & Science
基 金:"十三五"国家重点研发计划(2016YFB1000401);核高基重大转型"超级计算机处理器研发"(HGJ20152X01028101)
摘 要:指令流发射和指令Cache失效是处理器能量耗散的两个重要原因。松耦合的RISC指令集所产生的程序加剧了这样的能耗,而在片上Cache有限的网络设备如路由器、交换机中,因为指令流而遭受的性能下降和功耗增加更为严重。面向网络报文转发这一重要的网络功能服务,分析了网络报文转发的指令特性,并基于RISC-V指令集架构,重定制了RV32C压缩指令扩展集。经过Spike模拟器测试,优化后压缩率缩减至70%,动态指令压缩率为90%,同时在同等Cache条件下,使用定制压缩指令的指令Cache失效率比标准RISC-V降低了30%~70%。Instruction stream delivery and instruction Cache failure are two of the important reasons for processor energy dissipation.Programs based on loosely coupled RISC instruction sets exacerbate such energy consumption.Cache-limited network devices such as routers and switches suffer more per-formance degradation and power consumption due to instruction related processing.This paper focuses on network packet forwarding,which is one of the most important network functions.Thought analy-zing instruction characteristics of network packet forwarding,we redefine the RV32 compressed instruc-tion extension set based on the RISC-V instruction set architecture and test it by Spike simulator.Ex-perimental results show that the optimized compression rate is reduced to 70%and the dynamic instruc-tion compression rate is 90%.Meanwhile,under the same Cache conditions,our RV32C set can reduce the instruction Cache failure by 30%?70%in comparison to the standard RISC-V set.
分 类 号:TP303[自动化与计算机技术—计算机系统结构]
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