LTE上行DFT硬件加速器的设计  

Design of DFT Hardware Accelerator Used in LTE Uplink

作　　者：孙远昕 秦水介[2] SUN Yuanxin;QIN Shuijie(School of Big Data and Information Engineering,Guizhou University,Guiyang 550025,China;Guizhou Province of The Key Laboratory Optoelectronic Technology and Application,Guiyang 550025,China)

机构地区：[1]贵州大学大数据与信息工程学院,贵州贵阳550025 [2]贵州省光电子技术与应用重点实验室,贵州贵阳550025

出　　处：《电子科技》2018年第4期52-54,59,共4页Electronic Science and Technology

摘　　要：针对LTE上行链路离散傅里叶变换(DFT)预编码的多模式需求,提出了一种基于ASIC的DFT硬件电路实现方案。采用基于WFTA算法的基4/2/5/3蝶形运算单元实现35种长度的DFT运算,采用二维缓存结构实现蝶形单元流水处理。在200 MHz时钟频率、SMIC 40 nm工艺条件下,硬件电路面积为0.87 mm2,功耗为12.5 m W。仿真与综合结果表明,文中设计的DFT硬件加速器具有运算速度快、存储资源占用少的优点,适合于LTE工程应用。Aiming at the multi-mode requirement of DFT pre-coding in LTE uplink,a DFT hardware implementation scheme based on ASIC was proposed.Radix-4/2/5/3 butterfly unit based on WFTA algorithm was used to achieve 35 different lengths of DFT operation.The two-dimensional cache structure was utilized to achieve pipeline processing of butterfly unit.The chip occupied 0.87mm 2 core area and 12.5mW power consumption at 200 MHz frequency and SMIC 40 nm technology.The simulation and synthesis results showed that the DFT hardware accelerator had the advantages of high computing speed and less storage resources,which was suitable for LTE engineering applications.

关 键 词：LTE上行链路 DFT WFTA算法 ASIC 蝶形单元 流水处理 

分 类 号：TN47[电子电信—微电子学与固体电子学]