时钟脉冲上升沿时间对分频电路影响的实验研究与探讨  

Experimental Research and Discussion on the Influence of Clock Pulse Rising Time on Frequency Division Circuit

作　　者：邓己媛 黎长风 吴远泸 陈松 DENG Jiyuan;LI Changfeng,;WU Yuanlu;CHEN Song(College of Information Science and Engineering,Hunan Institute of Science and Technology,Yueyang 414006,China)

机构地区：[1]湖南理工学院信息科学与工程学院,湖南岳阳414006

出　　处：《湖南理工学院学报（自然科学版）》2018年第1期26-29,89,共5页Journal of Hunan Institute of Science and Technology(Natural Sciences)

基　　金：湖南省科技计划项目(2016TP1021);2017年湖南省大学生研究性学习和创新性实验计划项目(湘教通[2017]205号)

摘　　要：信号上升时间或下降时间对信号完整性的影响研究往往发生在高速系统中,笔者在中低速的模数接口分频电路中发现时钟脉冲信号上升沿时间直接决定了电路能否正常分频,提出除电平匹配和负载匹配是模数接口电路中通常考虑因素外,时钟信号沿陡峭程度也是电路正常工作不容忽视的输入影响因素.并对此进行了实验研究和探讨,提出了可行的解决方案.Signal rise time or fall time on signal integrity studies often occur in high-speed systems.The author is in the low-speed analog-digital interface circuit found that the rising edge of the clock pulse signal directly determines the frequency circuit can be normal,and for the first time,in addition to the level matching and load matching are the common factors in the analog-to-digital interface circuit,the steepness of the clock signal is also one of the input factors that can not be ignored in the normal operation of the circuit.The article conducts in-depth experimental study and discussion,and put forward a feasible solution.

关 键 词：时钟信号 上升沿时间 电平匹配 模数接口 影响因素 

分 类 号：TN11-34[电子电信—物理电子学]