用于DDR3访存优化的数据缓冲机制  

DDR3 data buffering for memory access optimization

作　　者：陈胜刚[1,2] 付兴飞 曾思 刘胜[1] CHEN Shenggang;FU Xingfei;ZENG Si;LIU Sheng(College of Computer,National University of Defense Technology,Changsha 410073,China;National Laboratory for Parallel and Distributed Processing,Changsha 410073,China)

机构地区：[1]国防科技大学计算机学院,湖南长沙410073 [2]并行与分布处理国家重点实验室,湖南长沙410073

出　　处：《国防科技大学学报》2017年第6期39-44,共6页Journal of National University of Defense Technology

基　　金：国家自然科学基金资助项目(61402499;61602493;61402500;61672526)

摘　　要：为提高DDR3控制器访存效率,设计了基于DDR3存储器预取访问数据长度的数据缓冲机制,将访存请求分为三种基本类型并分别排队处理,降低数据丢弃和实际动态随机访问存储器访问发生次数。针对图像和视频类应用程序的实验结果表明,相对于传统先到先服务的DDR3访存控制器,该机制取得了平均21.3%、最好51.3%的性能提升,硬件开销在可接受范围内。In order to improve the memory access efficiency of the DDR3 memory controller,adata buffering mechanism based on DDR3 memory access burst length was proposed.The application requests were guided into three different queues.The data buffering mechanism can make use of the additional data obtained from DRAM(dynamic random access memory)in one of the former request,thus reducing the actual external DRAM access needed.Experiments on several image and video application show that the proposed mechanism can improve the memory controller by an average 21.3%and a peak by 51.3%at an acceptable hardware cost when compared with the FCFS(first-come-first-serve)baseline DDR3 memory controller.

关 键 词：DDR3控制器 访存优化 数据缓冲 

分 类 号：TN95[电子电信—信号与信息处理]