DDR3上的双读写通道设计与实现  

Design and Implementation of the Double Read/Write Channels on DDR3

作　　者：唐瑞[1] 叶李萍 王经坤 姚远程[1] TANG Rui;YE Liping;WANG Jingkun;YAO Yuancheng(School of Information Engineering,Southwest University of Science and Technology,Mianyang 621010,China;School of Business,China West Normal University,Nanchong 637000,China)

机构地区：[1]西南科技大学信息工程学院,四川绵阳621010 [2]西华师范大学商学院,四川南充637000

出　　处：《自动化仪表》2018年第4期14-17,共4页Process Automation Instrumentation

基　　金：国家重大科学仪器设备开发基金资助项目(2016YFF0104003)

摘　　要：针对DDR3的灵活性与使用效率问题,提出了一种DDR3上的双读写通道设计与实现策略。在DDR3上切割出两套独立读写通道,基于时分复用(TDM)原则,使每套读写状态互不影响,能按要求完成用户任意读写指令。设计了一种时分复用桥接电路,通过数据切换器,使两套用户读写接口分时的与DDR3控制器接口相连接。将DDR3 IP核MIG提供的一套控制接口搭建为两套独立的用户读写接口,分时间片轮循执行用户读写命令,能总体实现对DDR3的同时读写操作。板级测试表明,DDR3内部读写时钟达800 MHz,外部用户接口操作时钟达200 MHz,用户数据位宽达256 bit,能满足用户同时读写的要求。该策略有助于解决各种高速实时数据缓存问题,具有广泛的应用价值。Aiming at the flexibility and efficiency of DDR3,a design and implementation strategy of double read/write channels on DDR3 is proposed.Two sets of independent read/write channels are cut on DDR3,and based on time division multiplexing(TDM)principle,each channel is not affected by another one;they can complete any read/write instruction of user.The TDM bridging circuit is designed;two user’s read/write interface is connected with DDR3 controller interface through the data switcher in time sharing mode.With the control interface provided by DDR3 IP core MIG,two independent user’s read/write interfaces are built,and the user’s read/write operations are carried out in time sharing,on the whole,DDR3 can read/write at the same time.The board level tests indicate that DDR3’s internal read/write clock reaches 800 MHz,external user interface operation clock reaches 200 MHz,data bit width of user reaches 256 bit,the simultaneous read/write requirement of user can be satisfied.The strategy solves various high speed and real time data cacheissues,and possesses wide applicable values.

关 键 词：DDR3控制器 单片机 双读写通道 时分复用 桥接电路 数据切换 

分 类 号：TH7[机械工程—仪器科学与技术] TP332[机械工程—精密仪器及机械]