SoC系统超低功耗设计方法  

Ultra Low Power Design Method for SoC System

作　　者：杨瑞瑞 何涛 唐伟文 范伟力 YANG Rui-rui;HE Tao;TANG Wei-wen;FAN Wei-li(Chengdu 30Javee Microelectronics Co.,Ltd.,Chengdu Sichuan 610041,China)

机构地区：[1]成都三零嘉微电子有限公司,四川成都610041

出　　处：《通信技术》2018年第4期967-972,共6页Communications Technology

摘　　要：随着芯片工艺线的不断发展,CMOS集成电路的特征尺寸不断缩小,集成电路的规模越来越大。但是,使用在便携式系统、智能卡领域的芯片却对功耗越来越严格,功耗消耗已经是衡量一款芯片成功与否的重要指标。因此,提高芯片的动态能耗比和降低芯片的待机静态功耗,是业界亟待解决的技术之一。从So C系统设计的角度出发,介绍了流水线设计、存储器分块访问、无复位端DFF寄存器的使用、系统时钟门控和后端物理低功耗实现等降低系统动态功耗的方法,和多阈值电压、电源门控、管脚和模拟器件静态功耗优化等降低芯片静态功耗的方法,并将其成功应用在了某款超低功耗专用安全芯片设计中。With the continuous development of chip process line,the feature size of CMOS is continuously shrinking,and the scale of integrated circuits is increasing.At the same time,the use of chips in the field of portable systems and smart cards has become increasingly stringent in terms of power consumption,and power consumption has become an important indicator of the success or failure of a chip.Therefore,improving dynamic energy ratio and reducing standby static power consumption of the chip is one of the technologies that need to be solved urgently in the industry.From the point of view of SoC system design,the method of reducing the dynamic power consumption of the system is introduced such as pipeline design,memory block access,use of non-reset DFF registers,system clock gating and back-end physical low-power implementation.Meanwhile,methods to reduce the static power consumption of the chip,such as multithreshold voltage,power gating,pin and analog device static power optimization,are introduced.Finally,these methods have been successfully applied to the design of an ultra-low power consumption dedicated security chip.

关 键 词：SOC系统 芯片 动态功耗 静态功耗 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]