基于三层级低开销的FPGA多比特翻转缓解技术  

Three abstraction levels based low overhead scheme of multiple bit upsets mitigation for FPGA

作　　者：张小林[1] 丁磊[1] 顾黎明[1] Zhang Xiaolin;Ding Lei;Gu Liming(No.36 Research Institute of CETC,Jiaxing 314033,China)

机构地区：[1]中国电子科技集团公司第三十六研究所,浙江嘉兴314033

出　　处：《电子技术应用》2018年第4期61-64,68,共5页Application of Electronic Technique

基　　金：国家高技术研究发展计划(863计划)(2013AA7071020A)

摘　　要：商用现货型FPGA被认为是解决目前空间应用对处理能力需求不断增加的唯一途径,由于其对多比特翻转的敏感性,需要针对空间应用的单粒子效应采取专门的设计加固技术。提出了基于用户逻辑层、配置存储器层和控制层3个层级的容错技术框架。在用户逻辑层,提出了一种新型的低开销的FTR策略用于用户逻辑的错误检测;在配置存储器级,提出了基于模块和帧的动态部分可重构策略用于处理配置存储器的错误;在控制级,以Xilinx ZYNQ片上系统型FPGA为目标,利用其嵌入的硬核处理器进行基于检查点和卷回体制的电路状态保存和恢复。整个容错技术框架在7级流水的LEON3开源器处理器中进行了故障注入的试验验证,试验结果显示在增加85%的LUT资源和125%的触发器资源使用条件下,99.997%注入的故障得到了及时纠正。Commercial-off-the-shelf(COTS)FPGAs are often advocated as the only solution to the increasing performance requirements in space applications.It also increases the circuit sensitivity to multiple bit upsets(MBU),thus specific design techniques must be applied to compensate this effect.This work tackles fault tolerance along three abstraction levels:user logic,configuration memory and control.At the user logic level,a new ultra-low overhead forward temporal redundancy(FTR)scheme is proposed for error detection in user logic.At the configuration memory level in the FPGA,this work leverages the opportunities brought by frame-and module-based dynamic partial reconfiguration(DPR)to handle configuration memory errors.At the control level,this work fully exploits the modern Xilinx ZYNQ system-on-chip FPGA which embeds a hard processor used for circuit state preservation with checkpointing and rollback.The overall topology is successfully validated with 99.997%reliability through fault-injection for a seven pipelined LEON3 processor at a global resource overhead only 85%in LUTs and 125%in flip-flops.

关 键 词：容错 多比特翻转 动态部分重构 时间冗余 

分 类 号：TN47[电子电信—微电子学与固体电子学]