基于FPGA的数字时钟管理电路设计应用  

Design and Application of Digital Clock Management Circuit Based on FPGA

作　　者：刘立岩 LIU Li-yan(The 723 Institute of CSIC,Yangzhou 225101,China)

机构地区：[1]中国船舶重工集团公司第七二三研究所,江苏扬州225101

出　　处：《舰船电子对抗》2018年第1期110-113,共4页Shipboard Electronic Countermeasure

摘　　要：介绍了运用现场可编程门阵列(FPGA)进行数字时钟管理方法的流程和应用。从FPGA设计入手,选用了Xilinx公司的Virtex-Ⅱ芯片系列,运用高精度数字时钟管理电路,保证延迟时间,通过仿真,得到移相后的各个时钟及等效时钟,得出了测量误差,满足时间精度要求,可应用于各高精度脉宽测量领域,能够满足各测量领域的设计要求。Abstract:This paper introduces the flow and application of digital clock management method based on field programmable gate array(FPGA)starting from FPGA design,adopts the Virtex-Ⅱchip serial of Xilinx Company,uses digital clock management circuit with high accuracy to ensure delay time,gains each clock and equivalent clock after phase shift through simulation,and fetches the measurement error,which can satisfy the requirement of clock accuracy.It can be used in each high accuracy pulse width measurement field and can satisfy the design requirement of each measurement field.

关 键 词：时钟管理 测量误差 脉宽测量 

分 类 号：TH714[机械工程—测试计量技术及仪器]