基于JESD204B协议的数据采集接口设计与实现  

Design and implementation of data acquisition interface based on the JESD204B protocol

作　　者：王红亮[1] 曹京胜 Wang Hongliang;Cao Jingsheng(Key Laboratory of Instrument Science&Dynamic Measurement,Ministry of Education,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室,太原030051

出　　处：《电测与仪表》2018年第7期87-91,共5页Electrical Measurement & Instrumentation

基　　金：国家自然科学基金资助项目(51425505)

摘　　要：目前国内对于高速串行JESD204B接口开发使用难以摆脱国外限制,缺乏自主设计技术经验积累。为了促进JESD204B接口国产化进程,文中介绍了一种基于JESD204B协议的高速采样数据解析接收电路。利用Xilinx的高速串行收发器GTX实现了JESD204B接口的物理层,采用GTX内部8B/10B译码器解析接收串行数据流,按照4拜特对齐方式完成字节对齐,对GTX的功能配置和端口信号进行了研究;通过FPGA逻辑设计完成了接口的链路层,采用模块化设计思想,设计了同步请求管理模块,通过判断连续接收到标识符的数目控制链路初始化,并设计了用于检测和替换数据帧尾控制字节的接收数据处理模块。经过测试验证,在7.4 Gbps的传输速率下接口可以正确解析数据,所设计接口电路满足工程应用需求。At present,the development of high-speed serial JESD204B interface is difficult to get rid of foreign restrictions and lack of independent design technical experience.In order to promote the localization process of JESD204B interface,this paper introduces a high-speed sampling data analysis and receiving circuit based on the JESD204B protocol.The physical layer of JESD204B interface is achieved by Xilinx high-speed serial transceiver GTX,and the 8b/10B decoder within the GTX is used to decode serial data stream,which is aligned byte according to the 4 byte alignment.So configuration and the function of the GTX port signal are studied.The link layer of the interface is completed through the FPGA logic design,adopting modular design thinking,a synchronous request management module is designed,which completes link initialization through the judgment receives the identifier of the number of consecutive,and the receive data processing module is designed to detect and replace the data frame tail control byte.After testing and verification,the interface can correctly analyze data at 7.4 Gbps transmission rate,and the design interface circuit meets engineering application requirements.

关 键 词：JESD204B 高速串行协议 GTX 数据采集 

分 类 号：TM93[电气工程—电力电子与电力传动]