低功耗浮点FFT处理器的设计  

Design of a low power floating point FFT processor

作　　者：杨琳琳 王新胜[1] 王静[1] YANG Linlin;WANG Xinsheng;WANG Jing(School of Information and Electrical Engineering,Harbin Institute of Technology,Weihai Shandong 264209,China)

机构地区：[1]哈尔滨工业大学信息与电气工程学院,山东威海264209

出　　处：《太赫兹科学与电子信息学报》2018年第2期352-356,共5页Journal of Terahertz Science and Electronic Information Technology

基　　金：中国博士后科学基金资助项目(2015M581447)

摘　　要：介绍了一种基于现场可编程门阵列(FPGA)的低功耗可配置浮点快速傅里叶变换(FFT)处理器的设计,可进行4点、16点、64点以及256点运算。采用按频率抽取的基–4算法和基于存储器的单蝶形结构。对蝶形运算单元进行优化,减少乘法器的数目,降低了功耗。存储单元采用乒乓存储结构,提高了数据的吞吐率。同时,采用浮点运算提高了处理器的运算精确度。该处理器采用中芯国际(SMIC)0.18μm工艺库进行综合,功耗为0.82 m W/MHz,并在ACX1329-CSG324FPGA上实现。A low power,configurable and floating-point Fast Fourier Transform(FFT)processor based on Field Programmable Gate Array(FPGA)is introduced.It can operate at 4,16,64 and 256 points.Radix-4 algorithm based on frequency extraction and single butterfly structures based on memory are utilized.Butterfly operation unit is optimized by reducing the number of multipliers,and the power consumption is reduced.The memory adopts the ping-pong storage structure,which improves the data throughput rate.The use of floating-point operations improves the computing accuracy of the processor.The design of processor is synthesized by using Semiconductor Manufacturing International Corporation(SMIC)0.18μm process library,and its power consumption is 0.62 mW/MHz.It is implemented on the ACX1329–CSG324 FPGA.

关 键 词：FFT处理器 浮点运算 低功耗 

分 类 号：TN911.72[电子电信—通信与信息系统]