锁相环陷波网络设计研究  

Notch network design with PLL method

作　　者：叶宝盛[1] 钱焕裕[1] 黄春良[1] YE Baosheng;QIAN Huanyu;HUANG Chunliang(No.36 Research Institute of CETC,Jiaxing 314033,China)

机构地区：[1]中国电子科技集团公司第三十六研究所,浙江嘉兴314033

出　　处：《湖北大学学报（自然科学版）》2018年第3期215-219,共5页Journal of Hubei University：Natural Science

摘　　要：对锁相环的陷波网络设计进行研究,提出一种借助CAD软件设计包含陷波网络的锁相环环路参数的新方法.由于实际元器件值的偏差,选择陷波宽度较宽的串联LC结构陷波网络更适合工程应用.但该结构对环路动态影响较大,锁相环容易进入失锁状态.通过CAD软件优化调整环路参数,补偿陷波网络的相移,将整体环路参数调回稳定状态,并在实际电路中得到验证.将鉴相杂散抑制由原来的-55 dBc提高到-78 dBc,解决环路带宽与鉴相杂散之间的矛盾,便于工程推广使用.A study of notch networks design was presented and a new notch networks design method with loop parameters in phase locked-loops with the help of CAD software was proposed in this paper.Due to the fact that the values of real components are fluctuant,it’s more suitable for engineering applications to choose a series trap wave network with wider notch width,but has a greater influence on the loop dynamics.By adjusting loop parameter using CAD tools and compensating the phase shift of notch networks,the whole loop parameters can be adjusted to stable state again.It is verified by the actual circuits and the spurious suppression at the phase detector frequency increased from-55 dBc to-78 dBc,solves the contradiction between the loop bandwidth and phase margin and it is easy to promote the use of engineering.

关 键 词：陷波网络 陷波滤波器 锁相环 

分 类 号：TB324.1[一般工业技术—材料科学与工程]