一种阵列众核处理器的多级指令缓存结构  

A multilevel instruction Cache structure for array-based many-core processor

作　　者：陈逸飞 李宏亮[1] 刘骁[1] 高红光[1] CHEN Yi-fei;LI Hong-liang;LIU Xiao;GAO Hong-guang(Jiangnan Institute of Computing Technology,Wuxi 214083,China)

机构地区：[1]江南计算技术研究所,江苏无锡214083

出　　处：《计算机工程与科学》2018年第4期571-579,共9页Computer Engineering & Science

基　　金：国家863计划(2015AA01A301);国家"核高基"重大专项(2013ZX01028001001001)

摘　　要：阵列众核处理器由于其较高的计算性能和能效比已经被广泛应用于高性能计算领域。而要构建未来高性能计算系统处理器必须解决严峻的"访存墙"挑战以及核心协同问题。通常的阵列处理器中,核心多采用单线程结构,以减少开销,但是对访存提出了较高的要求。在阵列众核处理器中,在单核心中引入硬件同时多线程技术,针对实验中一级指令缓存命中率随着线程数增加而显著降低的问题,提出了一种面向阵列众核处理器的冗余指令缓存存储结构,基于该结构,提出采用FIFO及类LRU替换策略。通过上述优化的高速缓存结构设计,经实验模拟,双线程整体指令Cache失效率降低了25.2%,整体CPI性能提升了30.2%。Because of their high computational performance and energy efficiency ratio,array-based many-core processors have been widely used in the high performance computing field.To build the future high performance computing systems,processors must solve the severe challenge of‘memory wall’and the core synergy problem.The kernel of the common array-based many-core processor uses a single-threaded structure to reduce the overhead,but the memory access demand is higher.In this paper,the hardware simultaneous multithreading technology is introduced into the single core structure.Aiming at the problem that the hit rate of the L1 instruction Cache is significantly reduced with the increase of the number of threads,this paper proposes an instruction Cache structure(Redundancy Instruction Cache)for the array-based many-core processors.Based on this structure,a FIFO replacement strategy and an analogous LRU replacement strategy are proposed.Experimental results demonstrate that,based on the optimized Cache structure design,the instruction Cache miss rate of the dual-threaded structure is decreased by 25.2%and the CPI performance is increased by 30.2%.

关 键 词：阵列众核处理器 同时多线程 冗余指令缓存 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]