具有小步进和低相噪的频率合成器的设计  

Design of frequency synthesizer with small step and low phase noise

作　　者：蒋佳男 马忠松[1] JIANG Jianan;MA Zhongsong(Key Laboratory of Space Application,Engineering and Technology Center for Space Utilization,Chinese Academy of Sciences,Beijing 100094,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院空间应用工程与技术中心,中国科学院太空应用重点实验室,北京100094 [2]中国科学院大学,北京100049

出　　处：《现代电子技术》2018年第16期9-12,共4页Modern Electronics Technique

摘　　要：为了设计具有小步进和低相噪的频率合成器,分析了直接式、锁相式和直接数字式频率合成器的优缺点,以及结合锁相环与直接数字式频率合成器的多种设计方案。在此基础上,使用DDS激励PLL的频率合成技术,设计了满足多种指标的频率合成器。该合成器的步进是1 Hz,当频率是10 k Hz时,合成器的相位噪声低于-90 d Bc/Hz,同时其输出带宽较大。A frequency synthesizer with small step and low phase noise is designed by analyzing the advantages and disadvantages of direct,phaselocked and direct digital synthesizers,and combining multiple design schemes of phaselocked loop and direct digital synthesizers.On this basis,the frequency synthesis technology using DDS to stimulate PLL is adopted to design the frequency synthesizer that can satisfy various indicators.The step of the synthesizer is 1 Hz,and when the frequency is 10 kHz,the phase noise of the synthesizer is lower than-90 dBc/Hz,and the output bandwidth of the synthesizer is relatively large.

关 键 词：频率合成 锁相环 低相噪 小步进 频率合成器 杂散 

分 类 号：TN73-34[电子电信—电路与系统] TN74