Chirp-Z变换FPGA流水架构设计与实现  

FPGA pipelined architecture design and implementation for Chirp-Z Transform

作　　者：孙健 韩文俊[1] 凌元[1] SUN Jian;HAN Wen-jun;LING Yuan

机构地区：[1]中国电子科技集团公司第十四研究所,江苏南京210013

出　　处：《信息技术与信息化》2018年第8期24-26,共3页Information Technology and Informatization

摘　　要：针对复数浮点Chirp-Z变换工程实现资源大、效率低的问题,文中提出了一种Chirp-Z变换的FPGA流水处理架构,通过分时复用Cordic单元进行Chirp-Z变换系数计算优化逻辑资源。实验结果显示,该架构FPGA实现的最高主频可达250MHz,平均通过率可达每秒100兆复数浮点数据。In order to solve the problem of large resource consumption and inefficiency in project implementation for complex float Chirp-Z transform,this paper presents an FPGA pipelined architecture,using the time-sharing multiplexing technology to calculate the Chirp coefficients and optimize the resource consumption.Implementation results show that this architecture can provide 250MHz clock frequency and achieve 100MSPS complex float data throughput.

关 键 词：CHIRP-Z变换 分时复用 FPGA 

分 类 号：TN791[电子电信—电路与系统]