适用于低功耗DC-DC变换器的双延迟线结构DPWM  

Dual Delay Line Structure DPWM for Low Power DC-DC Converters

作　　者：郑则炯[1] 梁文祯[2] ZHENG Zejiong;LIANG Wenzhen(School of Mechatronics,Guangdong Industry Polytechnic,Guangzhou 510335,China;Dept of Automation Engineering,Guangdong Polytechnic of Water Resources and Electric Engineering,Guangzhou 510925,China)

机构地区：[1]广东轻工职业技术学院机电技术学院,广州510335 [2]广东水利电力职业技术学院自动化工程系,广州510925

出　　处：《电子器件》2018年第4期877-881,共5页Chinese Journal of Electron Devices

基　　金：广东省重点科技项目(2015A023100007)

摘　　要：为了降低CMOS降压型DC-DC变换器的功耗,提出了一种双延迟线结构数字脉宽调制器DPWM(Digital Pulse Width Modulator)设计。该DPWM架构由双延迟线组成,可以降低功耗并通过改变分辨率来提高纹波电压。通过使用8位和16位延迟线实现了虚拟128位延迟线,并提出了相应的DPWM控制算法。基于180 nm TSMC CMOS工艺,采用Cadence软件进行仿真分析。仿真和实际测量结果表明,提出的双延迟链DPWM功耗为1.18μW,纹波电压为10.4 m V。工作频率100 k Hz时在4 m A^10 m A的负载电流范围内,与传统转换器相比,具有所提出DPWM的DC-DC变换器实现了较高的峰值效率92.8%,且有效面积较小。In order to reduce the power consumption of CMOS buck type DC-DC converter,a dual delay line structured digital pulse width modulator DPWM(Digital Pulse Width Modulator)is proposed.The DPWM architecture consists of double delay lines that reduce power dissipation and increase ripple voltage by varying resolution.The virtual 128 bit delay line is realized by using 8 bit and 16 bit delay lines,and the corresponding DPWM control algorithm is proposed.Based on the 180 nm TSMC CMOS process,Cadence software is used for simulation analysis.Simulation and actual measurement results show that the proposed double delay chain DPWM has a power dissipation of 1.18 W and a ripple voltage of 10.4 mV.Compared with the conventional converter,the proposed DPWM converter achieves a higher peak efficiency of 92.8%and a smaller effective area including a load current range of 4 mA^10 mA when operating frequency is 100 kHz.

关 键 词：DC-DC变换器 数字脉宽调制器 降压型变换器 延迟线 

分 类 号：TM446.43[电气工程—电器]