基于FPGA的NoC仿真器的设计与实现  

Design and implementation of NoC simulator based on FPGA

作　　者：王江峰[1] 宋庆增[1] 张静[1] 武继刚[2] WANG Jiangfeng;SONG Qingzeng;ZHANG Jing;WU Jigang(School of Computer Science and Software Engineering,Tianjin Polytechnic University,Tianjin 300000,China;School of Computers,Guangdong University of Technology,Guangzhou 510006,China)

机构地区：[1]天津工业大学计算机科学与软件学院,天津300000 [2]广东工业大学计算机学院,广东广州510006

出　　处：《现代电子技术》2018年第19期177-182,共6页Modern Electronics Technique

基　　金：高等学校博士学科点专项科研基金(20131201110002);国家科学自然基金(61672171)~~

摘　　要：片上网络的设计有很多功耗、面积和性能折中的拓扑结构、缓冲区大小、路由算法和流量控制机制,因此新的NoC设计的研究非常耗时。为了应对这些挑战,提出一种基于快速灵活的FPGA片上网络仿真架构,通过映射虚拟化的NoC组件到一个通用的片上网络仿真引擎上,其基础部件有流量生成器、路由、飞片队列等。并提出基于规则拓扑结构自动生成NoC拓扑结构的设想,且在设计的通用片上网络仿真引擎实施这种设想。实践表明:因为所设计的仿真器是虚拟的,可以模拟任何可用图描述的NoC拓扑结构;任何拓扑结构的片上网络可以映射到机器而无需重建,在一个大型片上网络设计中,用FPGA来实施可以节省很多时间。The design of the NoC includes the items of compromising topology between area and performance,buffer size,routing algorithms and flow control mechanisms,so the study on new NoC design will spend a lot of time.A NoC simulation architecture based on fast and flexible FPGA is proposed to overcome these challenges,which can map the virtualized NoC component to a commonly-used NoC simulation engine.The basic components of the architecture contains traffic generator,routing,flyer queues.A thought of automatic generation of NoC topology based on rule topology is proposed,and is implemented on a commonly-used NoC simulation engine.The virtualized NoC simulator can simulate any available NoC topology structures described by diagram,and NoC with any topology structure can be mapped to the machine without rebuilding.FPGA used to realize the NoC network can save a lot of time in a large-scale NoC design.

关 键 词：片上网络 FPGA 仿真器 拓扑结构 虚拟化 自动生成 

分 类 号：TN302-34[电子电信—物理电子学]