3.3V CMOS工艺下5V电源轨的ESD箝位电路  

ESD power-rail clamp circuit with a 5V power in the 3.3V CMOS process

作　　者：陈迪平[1] 董刚 CHEN Diping;DONG Gang(College of Physics and Microelectronics Science,Hunan Univ.,Changsha 4 10082,China)

机构地区：[1]湖南大学物理与微电子科学学院,湖南长沙410082

出　　处：《西安电子科技大学学报》2018年第5期96-101,共6页Journal of Xidian University

基　　金：国家自然科学基金资助项目(61474041)

摘　　要：基于传统栅极接地NMOS静电放电电源箝位结构,针对5V供电情况,通过电平移位及低漏电流续流措施,实现了3.3VCMOS集成电路工艺条件下5V电源轨的新型静电放电箝位电路,避免了高压工艺造成的成本增加.该电路采用分级驱动及分级泄放措施,降低了正常工作时电源箝位电路的漏电流.采用中芯国际0.18μm CMOS集成电路工艺库模型,仿真验证了电路的正确性;流片结果通过了人体模型±4 000V测试,该电路可成功用于5V电源轨静电放电保护.Considering the 5 V power supply,a novel ESD(electrostatic discharge)circuit with a 5 V power rail based on a conventional GG-NMOS(Gate-Ground NMOS)ESD power-rail clamp circuit is designed by the method of level shifters and the low follow current in the 3.3 V CMOS process to avoid a higher cost under the high-voltage process.Due to progressively driving and releasing steps of the optimized circuit,the leakage current is decreased in a regular operation.Moreover,the circuit is verified with simulations based on models in the SM!C5s 0.18^ni CMOS process technology library and the fabricated ESD power-rail clamp circuit has passed the HBM(Human Body Model)ESD test at±4 000 V.The circuits can be successfully used for the 5 V power rail ESD protection.

关 键 词：静电放电 保护电路 分级驱动 泄漏电流 

分 类 号：TN495[电子电信—微电子学与固体电子学]