支持指令预取的多核缓存WCET分析方法  

Cache WCET Analysis Method with Instruction Prefetching on Multi-cores

作　　者：安立奎[1] 韩丽艳[2] AN Likui;HAN Liyan(School of Mathematics and Physics,Bohai University,Jinzhou,Liaoning 121013,China;School of Information Science and Technology, Bohai University,Jinzhou,Liaoning 121013,China)

机构地区：[1]渤海大学数理学院,辽宁锦州121013 [2]渤海大学信息科学与技术学院,辽宁锦州121013

出　　处：《计算机工程》2018年第10期85-94,100,共11页Computer Engineering

基　　金：辽宁省科学技术计划项目"面向复杂海量数据的信息获取方法研究"(LN2014160)

摘　　要：为确保硬实时任务满足时间截止期,需要分析硬实时任务的支持指令预取缓存,而现有方法多数仅限于单级指令缓存,不能用于嵌入式多核下支持指令预取的多级缓存分析。为此,在基于组缓存划分的多核模型下,通过对抽象解释的缓存分析模型进行指令预取语义扩展,提出一种支持指令预取的多核缓存分析方法。实验结果表明,该方法安全性较高,能够提高多核下硬实时任务的预取缓存性能。In order to ensure Hard Real-time Task(HRT)to meet deadlines,their Worst Case Execution Time(WCET)with instruction prefetching need to be analyzed.Although the cache analysis methods with instruction prefetching in single-core have already existed,the researches are limited on the single-level instruction cache and they cannot be applied on the multi-level cache WCET analysis on multi-cores.Through extending instruction prefetching semantic for multi-level cache analysis model based on abstract interpretation,this paper puts forward a cache analysis method with instruction prefetching on the multi-cores model based on set cache partitioning.Experimental results verify the method has high safety and can improve the prefetching cache performance of multi-core HRT.

关 键 词：嵌入式多核 硬实时任务 最差情况执行时间 指令预取 缓存划分 

分 类 号：TP314[自动化与计算机技术—计算机软件与理论]