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作 者:蒋晓东 于纪言 Jiang Xiaodong;Yu Jiyan(Minsterial Key Laboratory of ZNDY,Nanjing University of Science and Technology,Nanjing 210094,China)
机构地区:[1]南京理工大学智能弹药国防重点学科实验室,江苏南京210094
出 处:《电子技术应用》2018年第11期33-36,共4页Application of Electronic Technique
摘 要:为了解决现有制导武器中弹载计算机计算性能较弱和传感器底层数据交互复杂等问题,提高弹载计算机计算性能与硬件集成度,提出一种基于So C FPGA的新型通用弹载计算机设计方案。提出的So C FPGA通用弹载计算机硬件设计集成度显著提高,通过三种平台(ARM、DSP和So C FPGA)的运算耗时实验对比,在相同计算要求下,该弹载计算机并行运算加速方法运算耗时相较串行运算下降了一个数量级,为4 ms,得到较好的运算加速效果。结果表明,基于SoC FPGA的新型通用弹载计算机硬件集成度高、通用接口丰富,而且弹载程序运算满足现代武器制导的实时性与精确性要求。In order to solve the problem such as weak calculation performance and complex sensor data interaction of the missile-borne computer in the existing guided weapons,and to improve its computing power and hardware integration,a new design of the general missile-borne computer based on the SoC FPGA is proposed.The experiment results show that the new missile-borne computer has a significant improvement of hardware integration,meanwhile,the time-consuming experiments on three platforms(ARM,DSP and SoC FPGA)have also been done.The experiment results show that compared to the traditional serial calculation method,the operation time of the new type parallel acceleration program is 4 ms,which decreases by an order of magnitude and obtains better acceleration effect.The proposed new type of general missile-borne computer has a high integration and rich interface,and the program calculation can meet the real-time and precision requirements of modern weapon guidance.
关 键 词:弹载计算机 通用接口 并行加速 SoCFPGA HLS
分 类 号:TP36[自动化与计算机技术—计算机系统结构]
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