通信专用新型二维可配置协处理器架构研究  

A novel two-level reconfigurable communication-specific coprocessor architecture

作　　者：赵旭莹 李桓 王晓琴[2] 王东琳[2] ZHAO Xuying;LI Huan;WANG Xiaoqin;WANG Donglin(College of Computer and Control Engineering,University of Chinese Academy of Sciences,Beijing 100190,China;National ASIC Design Engineering Center,Institute of Automation,Chinese Academy of Sciences,Beijing 100190,China)

机构地区：[1]中国科学院大学计算机与控制学院,北京100190 [2]中国科学院自动化研究所国家专用集成电路设计工程技术研究中心,北京100190

出　　处：《哈尔滨工程大学学报》2018年第12期2011-2016,共6页Journal of Harbin Engineering University

基　　金：国家科技支撑计划(2014BAH32B00);中国科学院战略性先导科技专项(XDA06011000)

摘　　要：针对当前主流通信协处理器架构存在互连网络功耗较大、调度频繁等问题,提出一种面向通信处理器的新型二维可配置协处理器架构。第一维配置为工作模式和协处理器公共参数配置,由主处理器发起,协处理器实时响应;第二维配置为加速引擎私有参数配置,由主处理器离线完成。通过功耗评估模型,该架构总线互连网络功耗仅为主流通信处理器架构的1/3;对于无线通信标准数据帧处理,总线带宽占用比由6. 88%降到2. 05%。基于此架构,对面向基站的无线通信接收端协处理器进行了设计实现。在数据吞吐方面与TMS320C6670中加速引擎对比,其中viterbi译码器加速比为3. 3,turbo译码器加速比为2. 8,可满足人们不断增长的高速数据传输需求。The large power consumption of interconnected networks and frequent scheduling are problems in the current mainstream communication coprocessor architecture.To solve these problems,a novel two-level reconfigurable coprocessor architecture for communication processors is proposed in this paper.The first level configuration includes work mode and coprocessor common parameters,and it is initiated by the main processor.The coprocessor responds in real time.The second-level configuration includes private parameters for acceleration engines,and it is computed offline by the main processor.The power consumption of bus interconnection network is equivalent to a third of the typical communication processor architecture,as found using a power evaluation model.The bus bandwidth occupancy ratio is reduced from 6.88%to 2.05%for a standard data frame processing by clustering the acceleration engines.Based on this architecture,a wireless communication receiver coprocessor for base station is designed.Compared with the acceleration engine in the TMS320C6670,the speed-up ratio of Viterbi decoder is 3.3,while that of the turbo decoder is 2.8,in terms of data throughput.It can satisfy people′s increasing demand for high-speed data transmission.

关 键 词：协处理器架构 通信处理器 二维配置 工作模式 私有参数 总线互连功耗 带宽占用比 调度频率 

分 类 号：TN92[电子电信—通信与信息系统]