高效LDPC译码器的优化与FPGA实现  

Optimization and FPGA Implementation of Efficient LDPC Decoder

作　　者：薛文[1] 余海[1] 王建新[1] 束锋[1] Xue Wen;Yu Hai;Wang Jianxin;Shu Feng(School of Electronic and Optical Engineering,Nanjing University of Science and Technology,Nanjing,210094,China)

机构地区：[1]南京理工大学电子工程与光电技术学院,南京210094

出　　处：《数据采集与处理》2018年第6期1101-1111,共11页Journal of Data Acquisition and Processing

基　　金：国家自然科学基金(61472190)资助项目

摘　　要：针对高效LDPC译码器设计过程中的参数选择问题,提出了针对Turbo译码消息传播(Turbo decoding message passing,TDMP)译码算法的离散密度进化算法。利用这种离散密度进化算法对译码算法中的校正因子及量化精度进行了优化。与传统的通过数值仿真进行优化的方法相比,本文算法效率大大提高,且效果显著。测试结果表明,优化的定点化译码器与纯浮点仿真相比性能只相差0.1dB左右。在译码器实现结构设计中提出了一种基于分布式RAM的P消息循环存储结构,与传统的基于寄存器和Benes网络的存储器结构相比,资源消耗明显下降。在Xilinx公司的FPGA平台上进行了硬件实现与测试,结果表明与同类译码器相比在资源消耗和吞吐率上均有一定优势,是一种高效的LDPC硬件译码器。A discrete density evolution algorithm for Turbo decoding message passing(TDMP)decoding algorithm is proposed to solve the problem of fixed parameter selection in efficient LDPC decoder design.By using the discrete density evolution algorithm,the modification factors and the quantization precision in the decoding algorithm are optimized.Compared with the traditional method,the efficiency is greatly improved and the effect is significant.Experimental results show that the performance of the optimized fixed-point decoder is only about 0.1 dB worse compared with the pure floating-point simulation.In the structure design of the decoder,a P-message circular memory structure based on distributed RAM is proposed.Compared with the traditional memory structure based on register and Benes network,the resource consumption is obviously decreased.The hardware implementation and test on FPGA platform of Xilinx company show that it has some advantages in terms of resource consumption and throughput compared with the same kind of decoder,and it is an efficient LDPC hardware decoder.

关 键 词：准循环LDPC码 Turbo译码消息传播 离散密度进化 分层消息处理单元 P消息循环存储器 

分 类 号：TN911.22[电子电信—通信与信息系统]