基于FPGA的SCL译码算法优化与设计  

The optimization and design of SCL decoding algorithm based on FPGA

作　　者：廖海鹏 卿粼波[1] 滕奇志[1] 何小海[1] 邓媛媛[1] Liao Haipeng;Qing Linbo;Teng Qizhi;He Xiaohai;Deng Yuanyuan(School of Electronics and Information Engineering,Sichuan University,Chengdu 610065,China)

机构地区：[1]四川大学电子信息学院,四川成都610065

出　　处：《电子技术应用》2018年第12期1-4,8,共5页Application of Electronic Technique

基　　金：国家自然科学基金资助项目(61471248);四川省教育厅2014年研究生教育改革创新项目(2014-教-034);成都市产业集群协同创新项目(2016-XT00-00015-GX)

摘　　要：由于极化码被指出在二进制离散无记忆信道中具有实现其极限容量的理论性能,近年来极化码在通信领域的贡献日渐凸显。极化码的译码系统可采用软件或者硬件方式实现,其中使用软件方式时译码效率受限于CPU的串行处理模式,因此在具有并行工作模式的FPGA上进行极化码的译码实现对于通信系统来说具有非常大的意义。首先介绍了极化码的SCL译码算法;然后针对该算法进行优化从而提高译码效率,以及针对该算法在FPGA上的实现进行了定点量化的改进;最后对译码器进行硬件仿真,以及在FPGA上进行了实现与性能分析。实验结果表明该译码器在码长为512时译码最高频率为143.988 MHz,吞吐率为28.79 Mb/s。In recent years,the contribution of polarization code to communication field is becoming more and more prominent,because the theory of polarization code is proved to be able to achieve the channel limit capacity in BDMC.The decoding system of polarization codes can be realized by software or hardware,and the software decoding speed is limited by the CPU serial working mode.So it is of great value for the communication filed to implement the decoder of polarization code on FPGA with parallel working mode.Firstly the SCL decoding algorithm is introduced in this paper.Then the algorithm is optimized to improve the decoding efficiency,and the quantization improvement is carried out on FPGA.Finally,the hardware emulation of the decoder and the performance analysis are carried out on FPGA.The experimental results show that the maximum frequency of the decoder is up to143.988MHz,and the throughput is up to28.79Mb/s when the code length is512.

关 键 词：极化码 FPGA SCL译码 定点量化 

分 类 号：TN911.2[电子电信—通信与信息系统]