可重构阵列处理器中分布式Cache设计  

Design of the distributed Cache for reconfigurable array processor

作　　者：蒋林 刘阳 山蕊 刘鹏 耿玉荣 Jiang Lin;Liu Yang;Shan Rui;Liu Peng;Geng Yurong(School of Electronic Engineering,Xi′an University of Posts and Telecommunications,Xi′an 710121,China;School of Computer,Xi′an University of Posts and Telecommunications,Xi′an 710121,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安邮电大学计算机学院,陕西西安710121

出　　处：《电子技术应用》2018年第12期9-12,16,共5页Application of Electronic Technique

基　　金：国家自然科学基金项目(61772417;61272120;61634004;61602377);陕西省自然科学基金项目(2015JM6326);陕西省科技统筹创新工程项目(2016KTZDGY02-04-02);陕西省教育厅专项科研计划项目(17JK0689);陕西省重点研发计划(2017GY-060)

摘　　要：随着片上集成的处理器核数日益增多,可重构阵列处理器中的"存储墙"问题日益加剧,而传统采用多级共享Cache硬件设计复杂度高,并行访问度有限,难以满足可重构阵列处理器的访存需求。设计了一种本地优先、全局共享的"物理分布、逻辑统一"分布式Cache结构,该结构硬件开销小,并行访问性高。通过Xilinx公司的Virtex-6系列xc6vlx550T开发板对设计进行测试,实验结果表明,该结构相比于同类结构,平均延迟减少最高达30%,硬件开销仅为Cache容量的5%,最高可提供10.512 GB/s的访存带宽。With the increasing number of processor cores integrated on-chip,the problem of“storage walls”in reconfigurable array processors is increasing.Traditionally,the use of multi-level shared Cache hardware design has high complexity and limited parallel access,and it is difficult to meet the memory requirements of reconfigurable array processors.This paper designs a local-priority,global-shared“physical distribution,unified logic”distributed Cache structure.The hardware overhead of this structure is small and parallel access is high.The Xilinx Virtex-6series xc6vlx550T development board was used to test the design.The experimental results show that the average delay of proposed architecture is reduced by up to30%compared with the similar structure,and the hardware overhead is only5%of the Cache capacity.The maximum memory access bandwidth is10.512GB/s.

关 键 词：阵列处理器 可重构 存储结构 分布式Cache 并行访问 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]