AFDX队列管理器的设计与实现  

Design and Implementation of AFDX Queue Manager

作　　者：黄旭 乔庐峰 陈庆华 吴艳华 HUANG Xu;QIAO Lu-feng;CHEN Qing-hua;WU Yan-hua(Dept,of Communication Engineering,Army Engineering University of PLA,Nanjing Jiangsu 210001,China)

机构地区：[1]陆军工程大学通信工程学院,江苏南京210001

出　　处：《通信技术》2018年第12期3028-3032,共5页Communications Technology

摘　　要：为灵活合理地利用带宽和存储资源,设计了一种用于航空电子全双工以太网(AFDX)的队列管理器。设计中需要对128条虚拟链路进行管理,因此需要充足的缓冲资源。通过采用构建链表的方式,对每条虚拟链路动态建立队列,且针对每条链路自由设定门限,使得缓冲能够合理地得到使用;缓冲区采用固定分配和共享缓存相结合的方式,灵活地使用缓冲资源,从而提高资源利用率;管理器内各模块使用双端口RAM,可同时支持读写操作。整个设计在Xilinx xc7z020clg400-1FPGA平台上实现,采用ModelSim SE10.2c进行仿真分析。结果表明,该设计可以满足对128条虚拟链路的缓冲管理。In order to flexibly and reasonably utilize bandwidth and storage resources, a queue manager for avionics full duplex Ethernet(AFDX) is designed. In the design, 128 virtual links need to be managed, so sufficient buffer resources are needed. By constructing a linked list, each virtual link is dynamically queued, and the threshold is freely set for each link, so that the buffer can be used reasonably. The buffer uses a combination of fixed allocation and shared cache to flexibly use buffer resources, thereby improving resource utilization. Each module in the manager uses dual-port RAM to support both read and write operations. The entire design was implemented on the Xilinx xc7z020clg400-1 FPGA platform, using ModelSim SE10.2c for simulation analysis. The results indicate that the design can satisfy the buffer management of 128 virtual links.

关 键 词：队列管理 虚拟链路 FPGA 缓冲管理 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]