2-1MASH多位Sigma-Delta转换器设计  

2-1MASH multi-bit Sigma-Delta converter design

作　　者：陈鑫磊 辛晓宁[1] 黄鑫 CHEN Xin-lei;XIN Xiao-ning;HUANG Xin(College of Information Science and Engineering,Shenyang University of Technology,Shenyang 110870,China)

机构地区：[1]沈阳工业大学信息科学与工程学院,辽宁沈阳110870

出　　处：《电子设计工程》2018年第24期64-68,73,共6页Electronic Design Engineering

摘　　要：量化器位数为3位的级联结构调制器,整体电路采用全差分结构设计使用0.35μm工艺实现。应用数据权重平均算法有效降低了多位DAC对元件匹配性的要求,对于7.8125 kHz的基带信号,在500 kHz的时钟速频率下,实现了87 dB的信噪比。结合抽取滤波器及校准算法,输出结果的无噪声分辨率达到14.16位,模拟部分不需要进行任何修调。整体电路使用ADMS进行混合仿真,采用3.3 V单电源供电的条件下工作电流小于600μA。The number of quantizer bits of the cascaded modulator is 3 bits,and the overall circuit is designed using a fully differential structure using a 0.35μm process.The application of data weight average algorithm effectively reduces the multi-bit DAC's requirement for component matching.For a 7.8125 KHz baseband signal,a signal-to-noise ratio of 87 dB is achieved at a clock speed of 500 KHz.Combine the decimation filter and the calibration algorithm,the output results in a noise-free resolution of 14.16 bits,and the analog part does not require any trimming.The overall circuit uses ADMS for mixed emulation,and the operating current is less than 600μA with a single 3.3V supply.

关 键 词：SIGMA-DELTA调制器 CIC滤波器 数据权重平均算法 多位量化 MASH结构 

分 类 号：TN431[电子电信—微电子学与固体电子学]