使用PERC的ESD设计版图验证流程  

A ESD Layout Verification Flow Based On PERC

作　　者：王鑫 WANG Xin(Beijing Key Laboratory of RFID Chip Test Technology,CECHuadaElectronic Design Co.,Ltd.,BeiJing 102209,China)

机构地区：[1]射频识别芯片检测技术北京市重点实验室,北京中电华大电子设计有限责任公司,北京102209

出　　处：《中国集成电路》2018年第11期48-52,共5页China lntegrated Circuit

摘　　要：随着半导体加工工艺的不断进步,对于ESD保护设计的挑战越来越大。在版图设计质量对于ESD性能影响极大的前提下,如何通过用工具重复的方式代替人工检查的方式来提高设计物理验证效率,是增强设计质量的重中之重。现存市场上成熟稳定的验证工具很多,但是如果具体到某个特定设计上,则普遍体现出对于ESD需求支持并不充分,需要自己针对设计的需求进行二次定制的特点。针对于此,本文以一个具体案例为引子,通过阐述从提出需求到完成验证工具二次定制规则文件编写这一过程,探究PERC工具应用于ESD版图检查的具体方法。With the continuous improvement of semiconductor processing technology,the challenge of ESD(Electro-Static discharge)protection design is increasing.On the premise that the quality of layout design has great influence on the performance of ESD(Electro-Static discharge),it is one of the most important thing to improve the design quality by replacing the manual inspection by means of tool’s check.There are many mature and stable verification tools in the existing market,but if they are specific to a particular design,it is generally shown that the support for ESD(Electro-Static discharge)needs is not sufficient and needs to be customized again for the design requirements.Aiming at this,this article takes a specific case as the introduction,and explores the specific method of applying the PERC tool to the ESD(Electro-Static discharge)layout inspection by elaborating the process of writing the customizing rule files from theestablishment of requirement to the usage of the verification tool.

关 键 词：静电放电 PERC 版图设计检查 

分 类 号：TN302[电子电信—物理电子学]