一种锁相频率合成器电路的稳定性  

The Stability of A Phase-locked Frequency Synthesizer Circuit

作　　者：吴立丰 陈睿 揭海 WU Li-feng;CHEN Rui;JIE Hai(Science and Technology on Electronic Information Control Laboratory, Chengdu 610036, China)

机构地区：[1]电子信息控制重点实验室,成都610036

出　　处：《电子信息对抗技术》2018年第6期79-82,共4页Electronic Information Warfare Technology

摘　　要：频率合成器是电子系统的心脏,对一种应用于电子侦察系统中的锁相频率合成器在工作中的不稳定现象进行了深入研究,详细介绍了锁相频率合成器的工作原理,通过仿真以及实测,逐次深入分析了锁相环路的失锁原理、环路中分频电路分频错误的原因、以及负载对环路稳定性影响的机理,准确解释了此类锁相频率合成器在工作中不稳定的深层次机理。Frequency synthesizer is the key components of the electronic system.The instability of a phase locked frequency synthesizer used in the electronic reconnaissance system is studied.The working principle of PLL frequency synthesizer is analysised detailedly.Through simulation and experiment,the losing lock principle of the PLL,the reason of causing the frequency division circuit working wrong,the deep mechanism of the influence of load on the stability of the loop are analyzed successively.The deep mechanism of the PLL frequency synthesizer’s unstability in work is demonstrated accurately.

关 键 词：锁相频率合成器 稳定性 失锁 负载 

分 类 号：TN74[电子电信—电路与系统]