基于SoC FPGA的高速EDIB总线通信电路设计  

Design of High-speed EDIB Communication Circuit Based on SoC FPGA

作　　者：刘西恩 叶朝辉[2] 张利伟[2] 戴鹏 Liu Xien;Ye Zhaohui;Zhang Liwei;Dai Peng(Well-Tech R&D Institute, COSL, Langfang 065201,China;Tsinghua University)

机构地区：[1]中海油服油田技术研究院,廊坊065201 [2]清华大学

出　　处：《单片机与嵌入式系统应用》2019年第1期55-59,共5页Microcontrollers & Embedded Systems

摘　　要：针对当前石油测井领域普遍采用"DSP+FGPA"、"MCU+FPGA"等双芯片架构实现EDIB总线通信功能时存在的可靠性低、体积大、功耗大的问题,本文提出采用SoC FPGA架构实现该功能,并具体介绍了EDIB总线读写模块、上传数据通道模块以及下载命令通道模块的设计方法。实验结果表明,该设计满足应用要求。In the current oil well-logging field,the dual-chip architectures such as"DSP+FGPA"and"MCU+FPGA"are widely used to realize the EDIB bus communication function,which has the problems of low reliability,large volume,and large power consumption.The EDIB bus communication function using SoC FPGA architecture is proposed,and specifically introduces the design method of the EDIB bus reading and writing module,the upload data channel module,and the download command channel module.The experiment results show that the design meets the application requirement.

关 键 词：SOC FPGA EDIB 通信接口电路 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]