XC6SLX9的全数字锁相环片上系统设计  

Design of All-digital Phase-locked Loop System Based on XC6SLX9

作　　者：郭永刚 王世伟[1] 王剑祥 张俊[1] 朱丽丽 崔敬忠[1] Guo Yonggang;Wang Shiwei;Wang Jianxiang;Zhang Jun;Zhu Lili;Cui Jingzhong(Lanzhou Institute of Physics,China Academy of Space Technology,Lanzhou 730000,China)

机构地区：[1]中国空间技术研究院兰州空间技术物理研究所,兰州730000

出　　处：《单片机与嵌入式系统应用》2019年第1期60-63,68,共5页Microcontrollers & Embedded Systems

摘　　要：介绍了一种基于FPGA的全数字锁相环片上系统的设计原理与实现方法,并给出了详细测试结果。该系统基于FPGA芯片XC6SLX9,使用Verilog语言完成系统程序设计,将整个锁相环系统集成到FPGA芯片中,实现了全数字锁相环片上系统,该系统采用自上而下的层次化设计。测试结果表明,该锁相环设计方法可行,具有良好的性能。In the paper,the design principle and implementation method of all-digital phase-locked loop system on chip based on FPGA are introduced,and the detailed test results are given.The system is based on XC6SLX9.Verilog language is used to complete the program design.The whole system is integrated into the FPGA chip,and the all-digital phase-locked loop on-chip system is realized.The system adopts the top-down hierarchical design.The test results show the feasibility of the PLL design method,and also verify the good performance.

关 键 词：FPGA VERILOGHDL XC6SLX9 全数字锁相环 

分 类 号：TN91[电子电信—通信与信息系统]