优化内存系统能效的DRAM架构研究综述  

A survey of optimizing the energy efficiency of memory system on DRAM architectures

作　　者：展旭升[1,2] 包云岗 孙凝晖[1] Zhan Xusheng;Bao Yungang;Sun Ninghui(Institute of Computing Technology,Chinese Academy of Science,Beijing 100190;University of Chinese Academy of Sciences,Beijing 100049)

机构地区：[1]中国科学院计算技术研究所,北京100190 [2]中国科学院大学,北京100049

出　　处：《高技术通讯》2018年第9期794-812,共19页Chinese High Technology Letters

基　　金：863计划(2015AA0153032);国家重点研发计划(2016YFB1000201);国家自然科学基金(61420106013)资助项目

摘　　要：介绍了不同层次优化内存系统能效研究的现状,对通过修改动态随机存取存储器(DRAM)架构优化内存系统能效的研究进行了详细论述。概述了通过修改内存控制器和操作系统实现的高能效DRAM系统的研究。着重介绍了通过修改DRAM架构实现内存系统能效优化的研究,并将这些研究分为"低延迟的DRAM架构"和"低功耗的DRAM架构"两大类进行介绍,其中低延迟架构的研究包括优化关键操作、降低平均访存延迟以及提升请求并发度等3个方面;低功耗的架构研究包括细粒度激活、低功耗与低频率芯片、优化写操作、优化刷新操作以及多粒度访存等5个方面。最后给出了关于修改DRAM架构实现内存能效优化的总结和展望。The research status of optimizing the energy efficiency of memory systems in different levels is introduced,and the mechanisms of modifying DRAM architectures are discussed in detail.We outline the research on energy efficiency of DRAM systems by modifying memory controller and operating systems.We emphatically introduce the research about optimizing the energy efficiency through modifying the DRAM architecture.These studies are divided into two groups:‘low-delay DRAM architecture’and‘low-power DRAM architecture’.Low-latency architectures contains three aspects:optimizing key operations,reducing average access latency,and increasing requests concurrency.Low-power architecture studies include five types:fine-grained activation architecture,low-power and low-frequency chips,optimized write operations,optimized refresh operations,and multi-granularity access mode.We show the summary and prospect of optimizing the memory energy efficiency of DRAM architectures in the end.

关 键 词：内存 动态随机存取存储器(DRAM) 内存控制器 架构 能效 低延迟 低功耗 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]