一种带失调校准的高速高精度采样保持电路  

High-Speed and High-Precision Sample Hold Circuit with Offset Calibration

作　　者：尹勇生[1] 卫海燕 曾凤姣 周京 YIN Yong-sheng;WEI Hai-yan;ZENG Feng-jiao;ZHOU Jing(Institute of Microelectronics Design,Hefei University of Technology,Hefei 230009,China)

机构地区：[1]合肥工业大学微电子设计研究所,安徽合肥230009

出　　处：《仪表技术与传感器》2018年第12期91-95,100,共6页Instrument Technique and Sensor

基　　金：中央高校基本科研业务费专项资金项目(JD2016JGPY0003)

摘　　要：设计了一款基于0. 18μm CMOS工艺带失调校准的高速高精度两级采样保持电路。该电路选择开环双通道时间交织的采样保持架构,提高了整体采样保持电路的速率。通过采用高精度失调校准电路、改进的级间缓冲器以及栅压自举开关等来提高采样保持电路的精度。电路仿真结果表明,在电源电压为2 V,采样时钟为1. 6 GHz,输入信号频率为382. 8 MHz,第一级和第二级保持电容分别为0. 9 f F和0. 6 f F时,该电路的无杂散动态范围(SFDR)为85. 8 d B,总谐波失真(THD)为-81. 7 dB,有效位数(ENOB)为12. 6 Bits。A high speed and high precision two stage sample and hold circuit based on 0.18 μm CMOS process with offset calibration was designed.The circuit used an open loop two-channel time- interleaved architecture,which improved the speed of the overall sample and hold circuit.The accuracy of sample and hold circuit was improved by adopting high-precision offset calibration circuit ,modified interstage buffer and bootstrapped switch.Simulation results show that the supply voltage is 2 V.The sampling clock is 1.6 GHz and the input signal frequency is 382.8 MHz.When the first and second holding capacitance is 0.9 fF and 0.6 fF respectively, the circuit's SFDR is 85.8 dB,THD is -81.7 dB,ENOB is 12.6 Bits.

关 键 词：两级采样保持电路 失调校准电路 级间缓冲器 栅压自举开关 

分 类 号：TN47[电子电信—微电子学与固体电子学]