全差分环形放大器的流水线模数转换器设计  

Design of pipeline analog digital converter based on fully differential ring amplifier

作　　者：陈鸣 肖璟博 陈敏[1] 陈杰[1] CHEN Ming;XIAO Jingbo;CHEN Min;CHEN Jie(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;School of Microelectronics,University of Chinese Academy of Sciences,Beijing 100029,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学微电子学院,北京100029

出　　处：《哈尔滨工程大学学报》2019年第1期196-201,共6页Journal of Harbin Engineering University

基　　金：国家重点基础研究发展项目(2015CB352103)

摘　　要：为了实现低功耗流水线模数转换器,本文提出了一种新型全差分环形放大器,并基于它设计了一款10 bit40 MS/s流水线模数转换器。本文采用HHGRACE 0. 18μm 1P6M混合信号工艺完成电路设计,当差分输入频率为2. 001 95 MHz的正弦信号时,仿真得到有效位数为9. 74位,最大微分非线性±0. 5LSB,最大积分非线性为±0. 65 LSB,整个ADC功耗为5. 32 m W,实现了低功耗模数转换器的设计。This study aims to develop a low-power pipeline analog-to-digital converter(ADC).A new fully differential ring amplifier is developed and used to design a 10 bit 40MS/s pipeline ADC.The system is implemented with mixed signals by HHGRACE 0.18um 1P6M process technology.Simulation results indicate that for a 2.001 95 MHz sinusoid input,the system can achieve an effective number of bit of 9.74 bit,a maximum differential non-linearity of±0.5 LSB,a maximum integral non-linearity of±0.65LSB,and total ADC core power consumption of 5.32 mW.

关 键 词：环形放大器 流水线 模数转换器 全差分 有效位数 信号噪声失真比 

分 类 号：TN43[电子电信—微电子学与固体电子学]